View UPD16676GF-3BA_3048001.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1996 mos integrated circuit m m m m pd16676 1/16, 1/32 duty lcd controller/driver data sheet document no. s10561ej5v0ds00 (5th edition) date published june 1999 ns cp(k) printed in japan the mark ? ? ? ? shows major revised points. description m pd16676 is a controller/driver containing rams capable of full-dot lcd displays. one of these ic chips can drive the full-dot lcd up to 61-by-16 dots. these ics are the most suitable for kanji character or chinese character pagers, as well as graphic pagers, displaying 16-by-16 dots per character. features lcd driver with built-in display ram dot display ram: 2560 bits output: 61 segments & 16 commons 8-bit parallel interface oscillation circuit incorporated ordering information part number package m pd16676p chips m pd16676w wafer m pd16676gf-3ba 100-pin plastic qfp (14 x 20 mm) remark purchasing the above products in terms of chips per wafer requires an exchange of other documents as well, including a memorandum of the product quality. therefore, those who are interested in this regard are advised to contact an nec salesperson for further details. ?
data sheet s10561ej5v0ds00 2 m m m m pd16676 1. block diagram seg 0 seg 60 com 0 com 15 common driver segment driver common counter timing generator internal oscillator osc 1 osc 2 61-bit latch display data ram (2560 bits) column address decoder column address counter & register parallel interface command decoder line address decoder line preset register & counter ram read/write controller v lc1 v lc2 v lc3 v lc4 v lc5 v dd v ss db 0 -db 7 a0 e(/rd) r,/w(/wr) /reset m,/s fr 61 16 8 8 8 8 8 8 remark /xxx indicates active low si gnals.
data sheet s10561ej5v0ds00 3 m m m m pd16676 2. pin configuration (pad layout) 1 99 81 82 80 79 52 51 50 49 32 31 30 29 100 2
data sheet s10561ej5v0ds00 4 m m m m pd16676 3. pin connection pin no. pin symbol i/o pin no. pin symbol i/o 1com 5 output 51 seg 21 output 2com 6 output 52 seg 20 output 3com 7 output 53 seg 19 output 4com 8 output 54 seg 18 output 5com 9 output 55 seg 17 output 6com 10 output 56 seg 16 output 7com 11 output 57 seg 15 output 8com 12 output 58 seg 14 output 9com 13 output 59 seg 13 output 10 com 14 output 60 seg 12 output 11 com 15 output 61 seg 11 output 12 seg 60 output 62 seg 10 output 13 seg 59 output 63 seg 9 output 14 seg 58 output 64 seg 8 output 15 seg 57 output 65 seg 7 output 16 seg 56 output 66 seg 6 output 17 seg 55 output 67 seg 5 output 18 seg 54 output 68 seg 4 output 19 seg 53 output 69 seg 3 output 20 seg 52 output 70 seg 2 output 21 seg 51 output 71 seg 1 output 22 seg 50 output 72 seg 0 output 23 seg 49 output 73 a0 input 24 seg 48 output 74 osc 1 input 25 seg 47 output 75 osc 2 output 26 seg 46 output 76 e(/rd) input 27 seg 45 output 77 r,/w(/wr) input 28 seg 44 output 78 v ss 29 seg 43 output 79 db 0 input/output 30 seg 42 output 80 db 1 input/output 31 seg 41 output 81 db 2 input/output 32 seg 40 output 82 db 3 input/output 33 seg 39 output 83 db 4 input/output 34 seg 38 output 84 db 5 input/output 35 seg 37 output 85 db 6 input/output 36 seg 36 output 86 db 7 input/output 37 seg 35 output 87 v dd 38 seg 34 output 88 /reset input 39 seg 33 output 89 fr input/output 40 seg 32 output 90 v lc5 41 seg 31 output 91 v lc3 42 seg 30 output 92 v lc2 43 seg 29 output 93 m,/s input 44 seg 28 output 94 v lc4 45 seg 27 output 95 v lc1 46 seg 26 output 96 com 0 output 47 seg 25 output 97 com 1 output 48 seg 24 output 98 com 2 output 49 seg 23 output 99 com 3 output 50 seg 22 output 100 com 4 output
data sheet s10561ej5v0ds00 5 m m m m pd16676 4. pin coordinates chip size : 4.04 x 5.53 mm 2 pad size al area : 120 x 120 m m 2 pad size open area : 108 x 108 m m 2 pin no. x ( m m) y ( m m) pin no. x ( m m) y ( m m) pin no. x ( m m) y ( m m) 1 1771 - 2230 36 668.8 2517.2 71 - 1771 - 757.2 2 1771 - 2076 37 518.8 2517.2 72 - 1771 - 907.2 3 1771 - 1922 38 368.8 2517.2 73 - 1767.8 - 1149.4 4 1771 - 1768 39 218.8 2517.2 74 - 1767.8 - 1299.4 5 1771 - 1614 40 68.8 2517.2 75 - 1767.8 - 1489.4 6 1771 - 1460 41 - 81.2 2517.2 76 - 1767.8 - 1639.4 7 1771 - 1306 42 - 231.2 2517.2 77 - 1767.8 - 1839.4 8 1771 - 1152 43 - 381.2 2517.2 78 - 1767.8 - 1989.4 9 1771 - 998 44 - 531.2 2517.2 79 - 1767.8 - 2139.4 10 1771 - 844 45 - 681.2 2517.2 80 - 1767.8 - 2289.4 11 1771 - 690 46 - 831.2 2517.2 81 - 1745 - 2513.4 12 1771 - 536 47 - 981.2 2517.2 82 - 1595 - 2513.4 13 1771 - 382 48 - 1131.2 2517.2 83 - 1395 - 2513.4 14 1771 - 228 49 - 1281.2 2517.2 84 - 1245 - 2513.4 15 1771 - 74 50 - 1431.2 2517.2 85 - 1045 - 2513.4 16 1771 80 51 - 1771 2242.8 86 - 895 - 2513.4 17 1771 234 52 - 1771 2092.8 87 - 682.6 - 2513.4 18 1771 388 53 - 1771 1942.8 88 - 532.2 - 2513.4 19 1771 542 54 - 1771 1792.8 89 - 382.2 - 2513.4 20 1771 696 55 - 1771 1642.8 90 - 106.6 - 2513.4 21 1771 850 56 - 1771 1492.8 91 69.8 - 2513.4 22 1771 1004 57 - 1771 1342.8 92 219.8 - 2513.4 23 1771 1158 58 - 1771 1192.8 93 369.8 - 2513.4 24 1771 1312 59 - 1771 1042.8 94 569.8 - 2513.4 25 1771 1466 60 - 1771 892.8 95 719.8 - 2513.4 26 1771 1620 61 - 1771 742.8 96 952.4 - 2513.4 27 1771 1774 62 - 1771 592.8 97 1102.4 - 2513.4 28 1771 1928 63 - 1771 442.8 98 1252.4 - 2513.4 29 1771 2082 64 - 1771 292.8 99 1402.4 - 2513.4 30 1771 2236 65 - 1771 142.8 100 1552.4 - 2513.4 31 1418.8 2517.2 66 - 1771 - 7.2 32 1268.8 2517.2 67 - 1771 - 157.2 33 1118.8 2517.2 68 - 1771 - 307.2 34 968.8 2517.2 69 - 1771 - 457.2 35 818.8 2517.2 70 - 1771 - 607.2
data sheet s10561ej5v0ds00 6 m m m m pd16676 5. pin descriptions 5.1 power system pin symbol pin name pin no. i/o function description v dd power supply pin 87 power supply v ss ground 78 ground v lc1 to v lc5 reference power supply for drivers 90,91,92, 94,95 reference power supply for lcd driving 5.2 logic system pin symbol pin name pin no. i/o function description m,/s master/slave selection 93 input switches between the master chip and the slave chip. fr lcd to ac signal 89 input/ output exchanges synchronizing signals (lcd-to-ac signals) in connecting cascades. this pin is for output if the chip is the master, and for input if the chip is the slave. db 0 to db 7 data bus 79 to 86 input/ output data inputs/outputs a0 data/instruction switching 73 input this pin is used for switching between the display data and the instruction. high level : display data low level : instruction /reset reset and 68/80-series switching 88 input this pin performs reset at the edge of the low-level pulse. at that level, it performs switching 68/80 series modes. high level : 68 series mpu interface low level : 80 series mpu interface e(/rd) enable and read enable 76 input 68 series mode : enable signal 80 series mode : read enable signal r,/w(/wr) read/write and write enable 77 input 68 series mode : read/write signal 80 series mode : write enable signal osc 1 oscillation pin 74 input oscillation (connected with a register between osc 2 ) osc 2 oscillation pin 75 output oscillation (connected with a register between osc 1 ) 5.3 driver system pin symbol pin name pin no. i/o description seg 0 to seg 60 segment 72 to 12 output segment output pins com 0 to com 15 common 96 to 100, 1 to 11 output common output pins if the chip is a slave, these pins correspond to com 16 to com 31 .
data sheet s10561ej5v0ds00 7 m m m m pd16676 6. commands command /rd /wr a0 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 function 1display on/off 10010101110/1on/off of the whole display is performed independent of the display rams data or internal state. 1: on, 0: off (power save at static drive on) note 2display start line 100110 display start address (0 to 31) determines the ram line displayed on the uppermost line (com 0 ) of the display. 3 page address set 100101110 p ages (0 to 3) sets display ram pages in the page address register. 4 column(segment) address set 1000 column addresses (0 to 79) sets display rams column address in the column address register. 5 status read 0 1 0 b u s y a d c o n / o f f r e s e t 0000r eads status busy 1: during internal operation 0: ready status adc 1: clockwise output(normal rotation) 0: counterclockwise output (reverse) on/off 1: display off, 0: display on reset 1: being reset, 0: normal 6 display data write 1 0 1 write data displays the data bus data and writes it onto the display ram. accesses the display ram of a pre-specified address. after access, the 7 display data read 0 1 1 read data reads the data in the display ram onto the data bus. column address is incremented. 8adc select 10010100000/1this comm and is used to reverse the correspondence relationship between display rams column addresses and segment driver outputs. 0: clockwise output (normal rotation) 1: counterclockwise output (reverse) 9 static drive on/off 10010100100/1selects betw een the normal display operation and the static all-lamp-driven display. 1: static drive (power save) note 0: normal display operation 10duty select 10010101000/1selects betw een two different liquid-crystal cell driving duties. 1: 1/32 duty 0: 1/16 duty 11 read modify write 10011100000increments the column address counter only when writing the display data; but not when reading it. 12end 10011101110cancels r ead modify write mode 13reset 10011100010sets the display start line register to the first line. sets the column address counter and the page address register to 0. note if the static drive is turned on in the display off state, the machine is placed in the power save state.
data sheet s10561ej5v0ds00 8 m m m m pd16676 7. display ram map db 0 db 7 page 0 (640 bits) page 1 (640 bits) page 2 (640 bits) page 3 (640 bits) line address 31 24 23 16 15 8 7 0 079 column address
data sheet s10561ej5v0ds00 9 m m m m pd16676 8. line address circuit as is shown in figure 8-1, the line address circuit specifies the line address that corresponds to a com output for displaying the contents of display data ram. the display start line address set command specifies line address of to the com 0 output. the screen can be scrolled by dynamically changing the line address via the display start line address set command. figure 8-1. specification of display start line address in display data ram db 1 0 db 0 4fh 4eh 4dh 4ch 4bh 4ah 49h 48h 1 db 0 seg 0 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 53 seg 54 seg 55 seg 56 seg 57 seg 58 seg 59 seg 60 page address data adc page0 page2 page3 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh com 0 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com 16 com 17 com 18 com 19 com 20 com 21 com 22 com 23 com 24 com 25 com 26 com 27 com 28 com 29 com 30 com 31 db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 page1 0 0 0 1 1 0 1 1 line address com output 1ah 19h 18h 17h 16h 15h 14h 13h 35h 36h 37h 38h 39h 3ah 3bh 3ch 00h 01h 02h 03h 04h 05h 06h 07h lcd out column address db 0 remark com 16 to com 31 are valid in only 1/32 duty. ?
data sheet s10561ej5v0ds00 10 m m m m pd16676 9. electrical specifications absolute maximum ratings (t a = 25 c, v ss = 0 v) parameter symbol rating unit supply voltage v dd C0.3 to +6.5 v driver reference supply input voltage v lc1 to v lc4 v dd C13 to v dd +0.3 v driver reference supply input voltage v lc5 v dd C13 to +0.3 v logic system input voltage v in1 - 0.3 to v dd + 0.3 v logic system output voltage v out1 - 0.3 to v dd + 0.3 v logic system input/output voltage v i/o1 - 0.3 to v dd + 0.3 v driver system output voltage v out2 v lc5 C0.3 to v dd + 0.3 v operating ambient temperature t a - 40 to +85 c storage temperature t stg - 65 to +150 c cautions 1. if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. 2. ensure that the phase relationship is v dd 3 3 3 3 v lc1 3 3 3 3 v lc2 3 3 3 3 v lc3 3 3 3 3 v lc4 3 3 3 3 v lc5 . recommended operating range (v ss = 0 v) parameter symbol min. typ. max. unit supply voltage v dd 2.7 5.5 v reference supply voltage v lc1 to v lc4 v dd C12 v dd v reference supply voltage v lc5 v dd C12 0 v logic system input voltage v in1 0v dd v ?
data sheet s10561ej5v0ds00 11 m m m m pd16676 electrical characteristics (unless otherwise specified, t a = -4 -4 -4 -4 0 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol condition min. typ. note max. unit high-level input voltage v ih1 a0, db 0 to db 7 , e, r,/w 0.8 v dd v high-level input voltage v ih2 fr, m,/s, /reset 0.8 v dd v low-level input voltage v il1 a0, db 0 to db 7 , e, r,/w 0.2 v dd v low-level input voltage v il2 fr, m,/s, /reset 0.2 v dd v high-level input current i ih a0, e, r,/w, /reset 1 m a low-level input current i il a0, e, r,/w, /reset C1 m a high-level output voltage v oh1 i out = C3 ma, db 0 to db 7 , v dd = 4.5 to 5.5 v 0.8 v dd v high-level output voltage v oh2 i out = C2 ma, fr, v dd = 4.5 to 5.5 v 0.8 v dd v high-level output voltage v oh3 i out = C120 m a, osc 2 , v dd = 4.5 to 5.5 v 0.8 v dd v low-level output voltage v ol1 i out = 3 ma, db 0 to db 7 , v dd = 4.5 to 5.5 v 0.2 v dd v low-level output voltage v ol2 i out = 2 ma, fr, v dd = 4.5 to 5.5 v 0.2 v dd v low-level output voltage v ol3 i out = 120 m a, osc 2 , v dd = 4.5 to 5.5 v 0.2 v dd v high-level output voltage v oh1 i out = C1.5 ma, db 0 to db 7 , v dd = 2.7 to 4.5 v 0.8 v dd v high-level output voltage v oh2 i out = C1 ma, fr, v dd = 2.7 to 4.5 v 0.8 v dd v high-level output voltage v oh3 i out = C80 m a, osc 2 , v dd = 2.7 to 4.5 v 0.8 v dd v low-level output voltage v ol1 i out = 1.5 ma, db 0 to db 7 , v dd = 2.7 to 4.5 v 0.2 v dd v low-level output voltage v ol2 i out = 1 ma, fr, v dd = 2.7 to 4.5 v 0.2 v dd v low-level output voltage v ol3 i out = 80 m a, osc 2 , v dd = 2.7 to 4.5 v 0.2 v dd v high-level leak current i loh db 0 to db 7 , v in/out = v dd 3 m a low-level leak current i lol db 0 to db 7 , v in/out = v ss C3 m a driver output on resistor r on t a = 25 c, v dd = 5 v, v lc5 = v ss 7.5 k w driver output on resistor r on t a = 25 c, v dd = 3.5 v, v lc5 = v ss 50 k w static current consumption i dd0 1.0 m a dynamic current consumption i dd1 external clock: 18 khz 15.0 m a self-oscillation: r = 1.3 m w 30.0 m a dynamic current consumption i dd3 during access: t cyc = 200 khz 500 m a input capacitance c in t a = 25 c, f = 1 mhz 8.0 pf oscillator frequency f osc in self-oscillation, v dd = 5.0 v, r = 1.3 m w 2% 15 18 21 khz oscillator frequency f osc in self-oscillation, v dd = 3.0 v, r = 1.3 m w 2% 11 16 21 khz reset time t r /reset ? internal reset release 1.0 1000 m s remark the typ. value is a reference value when t a = 25 c.
data sheet s10561ej5v0ds00 12 m m m m pd16676 ac characteristics 1 (unless otherwise specified, t a = - - - - 4 0 to +85 c, v dd = 4.5 to 5.5 v) 80 series mpu read/write timing parameter symbol condition min. typ. max. unit address hold time t ah8 a0 10 ns address setup time t aw8 20 ns system cycle time t cyc8 /wr, /rd 1000 ns control pulse width t cc 200 ns data setup time t ds8 db 0 to db 7 80 ns data hold time t dh8 10 ns /rd access time t acc8 db 0 to db 7 , c l = 100 pf 90 ns output disable time t oh8 10 60 ns 68 series mpu read/write timing parameter symbol condition min. typ. max. unit system cycle time t cyc6 a0, r,/w 1000 ns address setup time t aw6 20 ns address hold time t ah6 10 ns data setup time t ds6 db 0 to db 7 80 ns data hold time t dh6 10 ns output disable time t oh6 db 0 to db 7 , c l = 100 pf 10 60 ns access time t acc6 90 ns enable pulse width read t ew e 100 ns write 80 ns
data sheet s10561ej5v0ds00 13 m m m m pd16676 ac characteristics 2 (unless otherwise specified, t a = - - - - 4 0 to +85 c, v dd = 2.7 to 4.5 v) 80 series mpu read/write timing parameter symbol condition min. typ. max. unit address hold time t ah8 a0 20 ns address setup time t aw8 40 ns system cycle time t cyc8 /wr, /rd 2000 ns control pulse width t cc 400 ns data setup time t ds8 db 0 to db 7 160 ns data hold time t dh8 20 ns /rd access time t acc8 db 0 to db 7 , c l = 100 pf 180 ns output disable time t oh8 20 120 ns 68 series mpu read/write timing parameter symbol condition min. typ. max. unit system cycle time t cyc6 a0, r,/w 2000 ns address setup time t aw6 40 ns address hold time t ah6 20 ns data setup time t ds6 db 0 to db 7 160 ns data hold time t dh6 20 ns output disable time t oh6 db 0 to db 7 , c l = 100 pf 20 120 ns access time t acc6 180 ns enable pulse width read t ew e 200 ns write 160 ns
data sheet s10561ej5v0ds00 14 m m m m pd16676 test point of switching characteristics v ih v ih v il v il v oh v oh v ol v ol input output waveforms of switching characteristics 80 series mpu read/write timing a0 db 0 - db 7 (write) db 0 - db 7 (read) /wr,/rd t ah8 t aw8 t dh8 t cc t ds8 t acc8 t oh8 t cyc8 68 series mpu read/write timing r,/w e db 0 - db 7 (read) db 0 - db 7 (read) a0 t ah6 t dh6 t oh6 t ds6 t ew t aw6 t cyc6 t acc6
data sheet s10561ej5v0ds00 15 m m m m pd16676 reset /reset t r internal status reset status osc osc 1/f osc
data sheet s10561ej5v0ds00 16 m m m m pd16676 10. application circuit example v dd m,/s a0, /reset, e,/rd, r,/w, /wr db 0 - db 7 4 8 61 seg 16 com m,/s osc 1 fr gnd 16 com osc 1 fr osc 2 lcd pd16676 master chip m pd16676 slave chip m 61 seg ?
data sheet s10561ej5v0ds00 17 m m m m pd16676 11. package drawing 80 81 50 100 1 31 30 51 s s 100 pin plastic qfp (14x20) item millimeters d f g i j 0.8 0.6 0.65 (t.p.) 0.15 17.2 0.2 q s100gf-65-3ba-4 note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. c 14.0 0.2 m 0.17 0.125 0.075 a 23.2 0.2 h 0.32 0.08 l 0.8 0.2 n 0.10 p 2.7 s 2.825 0.175 + 0.08 - 0.07 b 20.0 0.2 k 1.6 0.2 r5 5 m n detail of lead end i j f g h q r p k m l a b cd s ?
data sheet s10561ej5v0ds00 18 m m m m pd16676 12. recommended soldering conditions please consult with our sales offices for soldering conditions of the m pd16676. type of surface mount device m pd16676gf-3ba : 100-pin plastic qfp (14 x 20 mm) ?
data sheet s10561ej5v0ds00 19 m m m m pd16676 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd16676 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

▲Up To Search▲

Price & Availability of UPD16676GF-3BA

	To Download UPD16676GF-3BA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .